As is known, many of the storage devices currently available commercially provide for the memory internal logic control circuitry to be reset.
The reset signal is normally generated within the integrated storage circuit, and the activation of this signal is responsive to a decrease in the circuit supply voltage Vcc.
This manner of operation is of special importance to devices being supplied a programming voltage Vpp from outside which usually has a relatively high value, in excess of 10 volts. The most dangerous situation likely to be encountered by such devices is, in fact, a decrease in the supply voltage Vcc while the value of the programming voltage Vpp is held at a high. Under this condition, lacking an ability to control the logic circuitry operation, erasure or incorrect programming of the storage elements may occur.
To avoid such problems, currently available devices on the market are arranged to include threshold detection devices which are supplied the programming voltage Vpp and effective to detect a drop in the supply voltage Vcc below a predetermined minimum value. Such circuits activate the device resetting by disabling all the circuits connected to the relatively high programming voltage Vpp.
The operation of the detection circuits is only ensured, however, in the presence of a programming voltage Vpp which has a positive value above a predetermined minimum value.
An example of a detection circuit based on the above-outlined operation principles is to be found in U.S. Pat. No. 4,975,885, to "INTEL." The circuit described therein has an output which would signal a drop in the supply voltage Vcc below a threshold value of 3.7 volts, but only for higher values of the programming voltage than 4.5 volts.
However, the reset mode provided by the prior art circuits affords no control at the device power-on stage, i.e., as the supply voltage Vcc is brought from 0 up to a steady-state value.
This deficiency is quite serious because on turning on, and in the absence of the programming voltage Vpp, no reset signal would be generated. In this way, the initial state of the internal control logic remains undetermined.
To obviate this drawback, some devices provide for the storage reset signal to be driven from outside. For instance, the integrated storage circuit currently available commercially has a PWD (Deep Power Down) pin intended to minimize the circuit's power consumption. However, that PWD pin may also receive a reset signal activated by the user.
This is not an adequate solution, because it depends on, among other things, the device user's proper recollection, skill and technical circuit knowledge.